S3C2410A20-YQ80
32-Bit RISC Microprocessor
FEATURES
Architecture
Integrated system for hand-held devices and
general embedded applications
16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core
Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux
Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect of
main memory bandwidth and latency on
performance
ARM920T CPU core supports the ARM debug
architecture.
Internal Advanced Microcontroller Bus Architecture
(AMBA) (AMBA2.0, AHB/APB)
System Manager
Little/Big Endian support
Address space: 128M bytes for each bank (total
1G bytes)
Supports programmable 8/16/32-bit data bus width
for each bank
Fixed bank start address from bank 0 to bank 6
Programmable bank start address and bank size
for bank 7
Eight memory banks:
– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/
Synchronous DRAM
Fully Programmable access cycles for all memory
banks
Supports external wait signals to expend the bus
cycle
Supports self-refresh mode in SDRAM for powerdown
Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, and others)
NAND Flash Boot Loader
Supports booting from NAND flash memory
4KB internal buffer for booting
Supports storage memory for NAND flash memory
after booting
Cache Memory
64-way set-associative cache with I-Cache (16KB)
and D-Cache (16KB)
8words length per line with one valid bit and two
dirty bits per line
Pseudo random or round robin replacement
algorithm
Write-through or write-back cache operation to
update the main memory
The write buffer can hold 16 words of data and four
addresses.
Clock & Power Manager
On-chip MPLL and UPLL:
UPLL generates the clock to operate USB
Host/Device.
MPLL generates the clock to operate MCU at
maximum 266MHz @ 2.0V.
Clock can be fed selectively to each function block
by software.
Power mode: Normal, Slow, Idle, and Power-off
mode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLL
Idle mode: The clock for only CPU is stopped.
Power-off mode: The Core power including all
peripherals is shut down.
Woken up by EINT[15:0] or RTC alarm interrupt
from Power-Off mode
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