MPC8321VRAFDC

 

 

High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for 

ATM or IP/Ethernet packet processing (or both).

• MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by 

supporting programmable protocol termination and network interface termination to meet evolving 

protocol standards.

• Single platform architecture supports the convergence of IP packet networks and ATM networks.

• DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1 

and DDR2.

• An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches, 

and dual integer units.

• Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus 

interface up to 66-MHz operation, and USB 2.0 (full-/low-speed).

• Security engine provides acceleration for control and data plane security protocols.

• High degree of software compatibility with previous-generation PowerQUICC processor-based 

designs for backward compatibility and easier software migration.

 

 

 

**注意 & Noted:

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