EP610PC-25 - High-performance, 16-macrocell Classic EPLD Pipelined data rates of up to 100 MHz - Rochester Electronics
High-performance, 16-macrocell Classic EPLD
- Combinatorial speeds with tPD as low as 10 ns
- Counter frequencies of up to 100 MHz
- Pipelined data rates of up to 100 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 Clock pins
The following devices are pin-, function-, and programming
file-compatible: EP610, EP610I, EP610T, EP610-XX/B, EP600I, and
PALCE610
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages (see Figure 1):
- 24-pin small-outline integrated circuit (plastic SOIC only)
- 24-pin dual in-line package (CerDIP and PDIP)
- 28-pin plastic J-lead chip carrier (PLCC)
**注意 & Noted:
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